韩银和，男，中国科学院计算技术研究所计算机体系结构国家重点实验室研究员，本科毕业于南京航空航天大学自动化学院，在中国科学院计算技术研究所取得工学博士学位后留所参加工作。

主要研究：容错和低功耗体系结构，互连体系结构。他已发表了20余篇SCI检索论文，40余篇EI检索论文，授权专利10项。他连续2年（2010，2011）在体系结构顶级会议ISCA上发表论文，在IEEE Trans on Computer等IEEE/ACM期刊上发表论文10余篇。他博士论文期间从事集成电路测试压缩研究，由于工作突出，他获得了中科院院长优秀奖、特别奖（各一项），中科院优秀博士论文，计算机学会优秀博士论文，全国百篇优秀博士论文提名（奖）。和同事一起，获得了北京市科学技术奖2项，中国计算机学会王选奖。

2001年获得南京航空航天大学工学学士学位，

2006年获得中国科学院计算技术研究所工学博士学位

2014年-，中科院计算所(计算机体系结构国家重点实验室),研究员

2008年9月-2014年，中科院计算所(系统结构重点实验室),副研究员

2006年3月-2008年9月，中科院计算所(先进测试技术实验室),助理研究员

计算机体系结构国家重点实验室

集成电路设计与测试、计算机容错结构设计，可重塑处理器

1.863探索类项目，“大规模多核处理器系统片上高性能互连技术研究”， 在研

2.国家自然科学基金面上项目，“片上网络芯片中路由器和互连线的测试方法研究”，在研

3.863探索类项目（副组长），“多处理器片上系统运行中低功耗关键技术研究”，在研

4.NSFC与香港RGC联合科研基金项目（陆方合作申请人之一），“片上系统测试架构设计与优化：针对噪声引起的测试良产率下降的研究”，在研

国际会议论文

2013

[C33]Hang Lu, Guihai Yan, Yinhe Han, Binzhang Fu, Xiaowei Li, “RISO: Relaxed Network-on-Chip Isolation for Cloud Processors”, Proc. of Design Automation Conference (DAC), 2013. (PDF)

2012

2011

[C30] Jianbo Dong, Lei Zhang, Yinhe Han, Xiaowei Li, “Wear Rate Leveling: Lifetime Enhancement of PRAM with Endurance Variation”, Proc. of IEEE/ACM Design Automation Conference (DAC), 2011.(PDF)

[C29] Jianliang Gao, Yinhe Han, Xiaowei Li, “Avoiding Data Repetition and Data Loss in Debugging Multiple-Clock Chips”, Will appear in Proc. of IEEE/ACM Design, Automation, and Test in Europe (DATE), 2011.(PDF)

[C28] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li and Xiaowei Li, “Smart Memory: exploiting and managing abundant off-chip optical bandwidth”, Will appear in Proc. of IEEE/ACM Design, Automation, and Test in Europe (DATE), 2011. (PDF)

[C27] Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li, “Vertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip”, Will appear in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), 2011.(PDF)

[C26] Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li, “A Resilient On-chip Router Design Through Data Path Salvaging”, Will appear in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), 2011.(PDF)

2010

[C25] Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng and Xiaowei Li, “nGFSIM : A GPU-Based Fault Simulator for 1-to-n Detection and its Applications”, Proc. of IEEE International Test Conference (ITC), paper 12.1, Nov. 2010.(PDF)

[C24]Song Jin, Yinhe Han, Huawei Li and Xiaowei Li, “P2CLRAF: An Pre- and Post-silicon Cooperated Circuit Lifetime Reliability Analysis Framework”, Proc. of IEEE Asian Test Symposium (ATS), 2010. (PDF)

[C23]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li and Xiaowei Li, “Address Remapping for Static NUCA in NoC-based Degradable Chip-Multiprocessors”, Proc. of IEEE Pacific Rim International Symposium on Dependable

Computing (PRDC), 2010. (PDF)

[C22] Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li , “Leveraging the Core-Level Complementary Effects of PVT Variations to Reduce Timing Emergencies in Multi-Core Processors”, Proc. of IEEE/ACM International Symposium on Computer Architecture (ISCA), 2010. (PDF)

[C21] Bingzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li , “Binary-Tree Waveguide Connected Time/Power Efficient Optical Network-on-Chip”, Proc. of IEEE/ACM Design, Automation, and Test in Europe (DATE), 2010. (PDF)

[C20] Lei Zhang, Yu Yue, Yinhe Han, Xiaowei Li, Shangping Ren ,”Performance-Asymmetry-Aware Topology Virtualization for Defect-tolerant NoC-Based Many-core Processors”, Proc. of IEEE/ACM Design, Automation, and Test in Europe (DATE), 2010.(PDF)

2009

[C19] Jun Liu, Yinhe Han, Xiaowei Li , “Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power”, Proc. of IEEE Asian Test Symposium (ATS), 2009.

[C18] Song Jin, Yinhe Han, Lei Zhang, Huawei Li , Xiaowei Li and Guihai Yan,” M-IVC: Using Multiple Input Vectors to Minimize Aging-induced Delay”, Proc. of IEEE Asian Test Symposium (ATS), 2009.(PDF)

[C17] Jianbo Dong, Lei zhang, Yinhe Han, Guihai Yan and Xiaowei Li , “Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy”, Proc. of IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), 2009.(PDF)

[C16] Bingzhang Fu, Yinhe Han, Huawei Li and Xiaowei Li ,”A New Multiple-Round DOR Routing for 2D Network-on-chip Meshes”,Proc. of IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), 2009.(PDF)

[C14] Guihai Yan, Yinhe Han, Xiaowei Li, “A Unified Online Fault Detection Scheme via Checking of Stability Violation”, Design, Automation and Test in Europe 2009. (PDF)

2008

[C12] Lei Zhang, Yinhe Han, Qiang Xu, and Xiaowei Li, “Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology,” IEEE/ACM Design, Automation and Test in Europe (DATE), pp. 891-896, 2008. (PDF)

2007

[C11] Lei Zhang, Yinhe Han, Qiang Xu, and Xiaowei Li, “Topology Reconfiguration Problem for Core-Level Redundancy in Homogeneous Chip Many-core Processors,” Fast Abstract, IEEE/IFIP International Conference on Dependable System and Networks (DSN), pp. 364-365, 2007. (PDF)

2006

[C9] Tong Liu, Huawei Li, Xiaowei Li, and Yinhe Han, “Fast Packet Classification using Group Bit Vector”, Proc. of 49th Annual IEEE Global Telecommunications Conference (Globecom2006), pp.1-5, 2006. (PDF)

[C8]Jie Dong, Yu Hu, Yinhe Han, Xiaowei Li, “An On-chip Combinational Decompressor for Reducing Test Data Volume”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS'06), May 21-24, 2006, Greece, pp.1459-1462

2005

[C7] Yinhe Han, Yu Hu, Xiaowei Li, and Huawei Li, “Using MUXs Network to Hide Bunches of Scan Chains,” in Proc. IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 238-243, May 2005. (PDF)

[C6] Yinhe Han, Yu Hu, Huawei Li, and Xiaowei Li, “Theoretic Analysis and Enhanced X-Tolerance of Test Response Compact based on Convolutional code,” in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 53-58, January 2005. (PDF)

[C5] Ji Li, Yinhe Han, Xiaowei Li, “Deterministic and Low Power BIST Based on Scan Slice Overlapping”, Proc. of IEEE of International Symposium on Circuits and Systems (ISCAS), May 2005, Kobe, Japan, pp.5670-5673. (PDF)

2004

[C4] Yinhe Han, Yu Hu, Anshuman Chandra, Huawei Li, and Xiaowei Li, “Rapid and Energy-Efficient testing for Embedded Cores,” in Proc. IEEE Asian Test Symposium, pp. 8-13, November 2004. (EI Access: 05078836557) (PDF)

[C3] Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, and Anshuman Chandra, “Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes,” in Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 298-305, Cannes, France, October 2004.(EI Access: 05399379765) (PDF)

[C2] Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li, “Pair Balance-Based Test Scheduling for SOCs”, Proc. of IEEE 13th Asian Test Symposium (ATS'04) , Kenting, November 15-17, 2004, pp.236-241. (PDF)

2003

[C1] Yinhe Han, Yongjun Xu, Anshuman Chandra, Huawei Li, and Xiaowei Li, “Test Resource Partitioning Based on Efficient Response Compaction for Test TArime and Tester Channel Reduction,” in Proc. IEEE Asian Test Symposium, pp. 440-445, November 2003. (PDF)

国际刊物论文

2012

2011

2010

[J20]Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan and Xiaowei Li, “Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling”, Journal of Systems Architecture, 56, 534-542, 2010.

[J19] Jianliang Gao, Yinhe Han, Xiaowei Li, “A Novel Post-Silicon Debug Mechanism Based on Suspect Window”, IEICE Transactions on Information and Systems, Vol.E93-D No.5 pp.1175-1185, 2010.

[J18] Jun Liu, Yinhe Han, Xiaowei Li, “Extended Selective Encoding for Reducing Test Data and Test Power”, IEICE Transactions on Information and Systems ,Vol.E93-D No.8, pp.2223-2232，2010.

2009

[J17] Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li and Huawei Li. “On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.17, pp.1173-1186, 2009. (PDF)

[J16] Wei Wang, Yin-He Han, Xiao-Wei Li, Fang Fang. “Co-optimization of Dynamic/Static Test Power in Scan Test”, Chinese Journal of Electronics. (PDF)

2008

[J15] Guihai Yan, Yinhe Han, Xiaowei Li, and Hui Liu, “BAT: Performance-Driven Crosstalk Mitigation Based on Bus-grouping Asynchronous Transmission,” IEICE Transactions on Electronic,E91-C(10), pp. 1690-1697, 2008. (PDF)

2007

[J14] Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, and Anshuman Chandra, “Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 15, No. 5, pp. 531-540, May 2007. (PDF)

[J13] Wang Wei, Hu Yu, Han Yinhe, Li Xiaowei, Zhang Yousheng，“Leakage Current Optimization Techniques during Test based on Don’t Care Bits Assignment，”Journal of Computer Science and Technology, Vol. 22, No. 5, pp. 673-680, 2007. (PDF)

2006

[J11] Yinhe Han, Xiaowei Li, Huawei Li, and Anshuman Chandra, “Embedded Test Resource for SoC to Reduce Required Tester Channels Based on Advanced Convolutional Codes,” IEEE Transactions on Instrumentation and Measurement, Vol. 55, No. 2, pp. 389-399, April 2006. (SCI IDS: 026IB, EI Access: 06149794655) (PDF)

[J10] Yinhe Han, Huawei Li, Xiaowei Li, and Anshuman Chandra, “Response Compaction for Test Time and Required TAM Width Reduction Based on Advanced Convolutional Codes,” Science In China: Serial F, Vol. 49, No.2, pp. 262-272, April 2006. (PDF)

[J9] Yu Hu, Yinhe Han, Xiao Li, Huawei Li, and Xiaoqing Wen, “Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time Received,” IEICE Transactions on Information and Systems, Vol. E89-D, No. 10, pp.2616-2625, Oct. 2006. (PDF)

2005

[J5] Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, and Xiaoqing Wen, “Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores,” IEICE Transactions On Information and Systems, Vol. E88-D, No.9, pp. 2126-2134, Sept. 2005. (SCI IDS: 967HJ, EI Access: 05429418698). (PDF)

[J4] Yinhe Han, Yongjun Xu, Anshuman Chandra, Huawei Li, and Xiaowei Li, “Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction,” Journal of Computing Science and Technology (JCST), pp. 201-210,20(2), Feb. 2005. (SCI IDS: 910GN,EI Access: 05209106292) (PDF)

2004

Workshop

2009

[W7] Dawen Xu, Yinhe Han, Huawei Li and Xiaowei Li, “A Fast and Memory-Efficient Fault Simulation Using GPU”, IEEE 10th Workshop on RTL and High Level Testing, 2009.

[W6] Song Jin, Yinhe Han, Lei Zhang, Huawei Li and Xiaowei Li, “On Predicting the Maximum Circuit Aging”, IEEE 10th Workshop on RTL and High Level Testing, 2010.

2008

[W4] Yinhe Han, Fang Fang, Wei Wang, Jianbo Dong, Xiaowei Li, Shanlin Yang, “Multicast Testing Method for NoC-based SoC Using Test Branches” IEEE 9th Workshop on RTL and High Level Testing, pp. 1-6, 2008. (PDF)

[W3] Binzhang Fu, Yinhe Han, Huawei Li and Xiaowei Li, “A New Methodology of reusing Network-on-Chip as Test-Access-Mechanism,” 2nd Workshop on Diagnostic Services in Network-on-Chips, pp.245-278, 2008. (PDF)

2007

2006

[W1] Wei Wang, Yinhe Han, Xiaowei Li, Yousheng Zhang, Yu Hu and Huawei Li, “PowerCut- A Novel Low-power scan testing”, Digest of Papers, IEEE 7th Workshop on RTL and High-Level Testing (WRTLT’06), July 23-24, 2006, Fukuoka, Japan, pp.49-54. (PDF)

2006年 中国科学院院长奖学金特别奖。

2005年 中国计算机学会创新奖“集成电路逻辑测试基础技术”（排名第三）

2003年 IEEE Asia Test Symposium最佳论文奖（IEEE Test Technology Technical Council 颁发）。

2005年 IEEE/ACM Asian South Pacific Design Automation Conference最佳论文奖提名，测试领域唯一。

2005年 获“中国科学院计算技术研究所所长特别奖”。

2005年 中国科学院计算技术研究所SONY奖。

1. 韩银和、李晓维，“一种单输出无反馈时序测试影响压缩电路”，专利号：ZL031490743, 授权日：2006年9月27日。

2. 韩银和，李晓维，“用于交流扫描测试中的片上快速信号生成电路”，专利号：ZL200410004831. 2，授权时间：2008年3月5日。

3. 韩银和，李晓维，“一种快速的集成电路测试流程优化方法”，专利号：ZL200410006727. 7，授权时间：2007年8月8日。

4. 韩银和，李晓维，“一种卷积码的编码方法” ，专利号：ZL200410045981. 8，授权时间：2008年2月6日。

5. 韩银和，李晓维，“一种应用于系统级芯片测试中的芯核并行包装电路和方法”， 专利号：ZL200410047572. 1，授权时间：2007年6月27日。